For the design of integrated circuits (ICs) (e.g., on the scale of Very Large Scale Integration (VLSI) technology), designers often employ computer-aided techniques. Standard languages such as Hardware Description Languages (HDLs) have been developed to describe digital circuits to aid in the design and simulation of complex digital circuits. Generally, hardware description languages, e.g., VHDL and Verilog allow definition of a hardware model at a gate level, a register transfer level (RTL) or a behavioral level using abstract data types. As device technology continues to advance, various product design tools have been developed to adapt HDLs for use with newer devices and design styles.
Typically, in designing an integrated circuit with an HDL code, the code is first written and then compiled by an HDL compiler. The HDL source code describes at some level the circuit elements, and the compiler produces an RTL netlist from this compilation. The RTL netlist is typically a technology independent netlist in that it is independent of the technology/architecture of a specific vendor's integrated circuit, such as field programmable gate arrays (FPGA) or an application-specific integrated circuit (ASIC). The RTL netlist corresponds to a schematic representation of circuit elements (as opposed to a behavioral representation). A mapping operation is then performed to convert from the technology independent RTL netlist to a technology specific netlist, which can be used to create circuits in the vendor's technology/architecture. It is well known that FPGA vendors utilize different technology/architecture to implement logic circuits within their integrated circuits. Thus, the technology independent RTL netlist is mapped to create a netlist, which is specific to a particular vendor's technology/architecture.
Integrated Circuits (ICs) are used in numerous applications, e.g., handheld devices, such as cellular phones, wristwatch cameras, organizers, and others. As the commercial markets and consumer demands for smaller Integrated Circuits grow, IC size requirement trends continue towards a small form factor and lowered power consumption.
Integrated circuits include millions of metal oxide semiconductor field effect transistors (“MOSFET”). The steady downscaling of MOS transistor dimensions has been the main stimulus to the growth of microelectronics and the computer industry over the past two decades.
Advanced integrated circuit device process technologies that provide submicron device feature sizes (e.g., no greater than 22 nanometers (nm)) can contain complex conductor geometries in a device region. The complex conductor geometries include, for example, multi-gate devices (e.g., FinFETs), trench contacts, raised source/drain regions (RSD), and other conductor geometries.
FIG. 1A is a perspective view of a FinFET transistor structure 100. The transistor structure has a source region 105 and a drain region 107 at opposite sides of the gate electrode 101. A portion of the gate 103 wraps around the fin. The gate electrode 101 with underlying gate dielectric covers the top and the two opposing sidewalls of the portion of the fin body 103. This effectively triples the space available to more effectively control the device channel in order to give the FinFET transistor substantially higher performance than the conventional planar transistors.
FIG. 1B is a perspective view of a multi-gate transistor structure 110. The multi-gate transistor structure 110 has a raised source region 117 and a raised drain region 115 having multiple fins on a substrate 113. As shown in FIG. 1B, a portion 112 of a gate 111 is formed over the fins connecting the raised source region 117 and raised drain region 115. As shown in FIG. 1B, structure 110 provides multiple gate channels over the fins of the raised drain/source regions 115 and 117.
FIG. 1C shows a device region layout in a traditional contact process 150. The traditional contact process involves creating a plurality of via-based contacts, such as via contacts 153 and via contacts 155. As shown in FIG. 1C, each of the via contacts 155 connects a lowest routing layer 151 (M1) and a diffusion 152 (e.g., source/drain regions). As shown in FIG. 1C, each of the via contacts 153 connects a lowest routing layer 156 (M1) to a poly gate 154.
Currently, most process technologies providing a feature size 22 nm and smaller have trench contacts in the device region. Trench contacts typically serve two purposes: they physically connect a lowest routing layer (e.g., M1 layer) to a poly (e.g., a gate contact) and physically connect a lowest routing layer (e.g., M1 layer) to the diffusion (e.g., source/drain contact regions) in the device region. In this capacity, trench contacts replace traditional via-like contacts.
FIG. 1D shows a device region layout in a trench contact process 160. As shown in FIG. 1D, in the trench contact process via contacts 155 are replaced by a trench contact 165, and via contacts 153 are replaced by a trench contact 163. Trench contacts can be used for local routing purposes between devices. Trench contacts have several advantages over standard via-based contacts including increased layout density, improved reliability and performance, and ease of patterning for sub-micron lithography.
Current process technologies that include the aforementioned advanced process features have several challenging characteristics for capacitance extraction. The process technologies with trench contacts can contain a large number (>10) of conducting layers. These conducting layers are in close proximity and have unique physical characteristics that provide a challenge for capacitance extraction of a large-scale integrated circuit design. Further, the advanced process features such as trench contacts, RSDs, and multi-gate device geometries are context dependent with respect to non-rectangular conductor geometries and conformal dielectric configurations. Furthermore, trench contact conductors can be used for local interconnect routing or inter-layer connectivity within a device. The capacitive behavior of trench contacts in these two scenarios is significantly different.
The existing methods can compute the capacitance associated with a given conductor geometry directly using numerical techniques. These methods, however, do not have sufficient speed or capacity for extracting large-scale designs.